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Single-Chip Passive UHF RFID Tags and Readers
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Phase 1
Objective:
The objective of this project is to develop enabling technologies for low-cost single-chip CMOS passive RFID tags in the UHF frequency range from 860 MHz to 960MHz. First, enabling technologies for passive RFID tags, including antennas, power management, ultra-low-energy digital design, non-volatile memory, and packaging - will be investigated. Second, these enabling technologies will be integrated for a low-cost solution. In parallel, suitable system architectures and building blocks for single-chip RFID readers will also be designed and demonstrated, including RFIC transceiver and baseband.
Project Specification and Challenge:
This project aims to develop enabling technologies for low-cost, single-chip RFID tags in the UHF range from 860 MHz to 960 MHz. The high operation frequency is more desirable compared to the HF range around 13.56 MHz used by existing solutions mainly because the potential of providing long-distance communication between the readers and the tags while minimizing the antenna size and cost.
Challenges in developing the tags are with all the enabling technologies. An array of sensitive readers will be needed to make the systems orientation-independent, and novel designs of tag antennas will be required to overcome the problem of signal blocking and attenuation. In parallel, integration of all the circuits required for the tags (including RF, power rectifier, charge pump, memory, and baseband) into a very-small-sized single chip for low-cost low-power solutions will also be essential. Finally, new packaging and assembly technologies need to be developed to handle billions of these tiny IC chips with suitable antennas.
Technological challenges in developing the readers include the design and integration of the RFIC transceiver and the baseband for low-cost, low-power single-chip solutions.